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slas241h ? september 1999 ? revised september 2004 1 post office box 655303 ? dallas, texas 75265 low supply voltage range 1.8 v to 3.6 v ultralow-power consumption ? active mode: 160 a at 1 mhz, 2.2 v ? standby mode: 0.7 a ? off mode (ram retention): 0.1 a wake-up from standby mode in less than 6 s 16-bit risc architecture, 125 ns instruction cycle time basic clock module configurations: ? various internal resistors ? single external resistor ? 32-khz crystal ? high-frequency crystal ? resonator ? external clock source 16-bit timer_a with three capture/compare registers on-chip comparator for analog signal compare function or slope a/d conversion serial onboard programming, no external programming voltage needed programmable code protection by security fuse family members include: msp430c1101: 1kb rom, 128b ram msp430c1111: 2kb rom, 128b ram msp430c1121: 4kb rom, 256b ram msp430f1101a: 1kb + 128b flash memory 128b ram msp430f1111a: 2kb + 256b flash memory 128b ram msp430f1121a: 4kb + 256b flash memory 256b ram available in a 20-pin plastic small-outline wide body (sowb) package, 20-pin plastic small-outline thin package, 20-pin tvsop (f11x1a only) and 24-pin qfn for complete module descriptions, refer to the msp430x1xx family user?s guide , literature number slau049 description the texas instruments msp430 family of ultralow power microcontrollers consist of several devices featuring different sets of peripherals targeted for various applications. the architecture, combined with five low power modes is optimized to achieve extended battery life in portable measurement applications. the device features a powerful 16-bit risc cpu, 16-bit registers, and constant generators that attribute to maximum code ef ficiency. the digitally controlled oscillator (dco) allows wake-up from low-power modes to active mode in less than 6 s. the msp430x11x1(a) series is an ultralow-power mixed signal microcontroller with a built-in 16-bit timer, versatile analog comparator and fourteen i/o pins. typical applications include sensor systems that capture analog signals, convert them to digital values, and then process the data for display or for transmission to a host system. stand alone rf sensor front end is another area of application. the i/o port inputs provide single slope a/d conversion capability on resistive sensors. available options packaged devices t a plastic 20-pin sowb (dw) plastic 20-pin tssop (pw) plastic 20-pin tvsop (dgv) plastic 24-pin qfn (rge) ?40 c to 85 c msp430c1101idw msp430c1111idw msp430c1121idw msp430c1101ipw msp430c1111ipw msp430c1121ipw msp430f1101aidgv msp430f1111aidgv msp430c1101irge msp430c1111irge msp430c1121irge ?40 c to 85 c msp430c1121idw msp430f1101aidw msp430f1111aidw msp430f1121aidw msp430c1121ipw msp430f1101aipw msp430f1111aipw msp430f1121aipw msp430f1111aidgv msp430f1121aidgv msp430c1121irge msp430f1101airge MSP430F1111AIRGE msp430f1121airge please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. copyright ? 1999 ? 2004 texas instruments incorporated
slas241h ? september 1999 ? revised september 2004 2 post office box 655303 ? dallas, texas 75265 rge package (top view) 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 test v cc p2.5/r osc v ss xout xin rst /nmi p2.0/aclk p2.1/inclk p2.2/caout/ta0 p1.7/ta2/tdo/tdi p1.6/ta1/tdi/tclk p1.5/ta0/tms p1.4/smclk/tck p1.3/ta2 p1.2/ta1 p1.1/ta0 p1.0/taclk p2.4/ca1/ta2 p2.3/ca0/ta1 dw, pw, or dgv package (top view) v ss p2.5/r osc xout v cc xin test rst /nmi p1.7/ta2/tdo/tdi p2.0/aclk p1.6/ta1/tdi/tclk nc nc p1.4/smclk/tc k p1.3/ta2 p1.2/ta1 p1.1/ta0 p1.0/taclk p1.5/ta0/tms note: nc pins not internally connected p2.1/inclk p2.2/caout/ta0 nc p2.3/ca0/ta1 p2.4/ca1/ta2 nc 1 2 3 4 5 6 18 17 16 15 14 13 891011 20 21 22 23 power pad connection to v ss recommended functional block diagram oscillator aclk smclk cpu incl. 16 reg. bus conv mcb xin xout p2 mdb, 16 bit mab, 16 bit mclk mab, 4 bit v cc v ss rst /nmi system clock r osc p1/jtag flash/rom 4kb 2kb 1kb ram 256b 128b 128b watchdog timer 15/16-bit timer_a3 3 cc reg i/o port 1 8 i/os, with interrupt capability i/o port 2 6 i/os, with interrupt capability por mdb, 16-bit mab, 16-bit test test jtag emulation module 8 6 comparator a mdb, 8 bit
slas241h ? september 1999 ? revised september 2004 3 post office box 655303 ? dallas, texas 75265 terminal functions terminal name dw, pw, or dgv rge i/o description name no. no. i/o description p1.0/taclk 13 13 i/o general-purpose digital i/o pin/timer_a, clock signal taclk input p1.1/ta0 14 14 i/o general-purpose digital i/o pin/timer_a, capture: cci0a input, compare: out0 output/bsl transmit p1.2/ta1 15 15 i/o general-purpose digital i/o pin/timer_a, capture: cci1a input, compare: out1 output p1.3/ta2 16 16 i/o general-purpose digital i/o pin/timer_a, capture: cci2a input, compare: out2 output p1.4/smclk/tck 17 17 i/o general-purpose digital i/o pin/smclk signal output/test clock, input terminal for device programming and test p1.5/ta0/tms 18 18 i/o general-purpose digital i/o pin/timer_a, compare: out0 output/test mode select, input terminal for device programming and test p1.6/ta1/tdi/tclk 19 20 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/test data input or test clock input p1.7/ta2/tdo/tdi ? 20 21 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/test data output terminal or data input during programming p2.0/aclk 8 6 i/o general-purpose digital i/o pin/aclk output p2.1/inclk 9 7 i/o general-purpose digital i/o pin/timer_a, clock signal at inclk p2.2/caout/ta0 10 8 i/o general-purpose digital i/o pin/timer_a, capture: cci0b input/ comparator_a, output/bsl receive p2.3/ca0/ta1 11 10 i/o general-purpose digital i/o pin/timer_a, compare: out1 output/ comparator_a, input p2.4/ca1/ta2 12 11 i/o general-purpose digital i/o pin/timer_a, compare: out2 output/ comparator_a, input p2.5/r osc 3 24 i/o general-purpose digital i/o pin/input for external resistor that defines the dco nominal frequency rst /nmi 7 5 i reset or nonmaskable interrupt input test 1 22 i selects test mode for jtag pins on port1. the device protection fuse is connected to test. v cc 2 23 supply voltage v ss 4 2 ground reference xin 6 4 i input terminal of crystal oscillator xout 5 3 o output terminal of crystal oscillator qfn pad na package pad na qfn package pad connection to v ss recommended. ? tdo or tdi is selected via jtag instruction.
general-purpose register program counter stack pointer status register constant generator general-purpose register general-purpose register general-purpose register pc/r0 sp/r1 sr/cg1/r2 cg2/r3 r4 r5 r12 r13 general-purpose register general-purpose register r6 r7 general-purpose register general-purpose register r8 r9 general-purpose register general-purpose register r10 r11 general-purpose register general-purpose register r14 r15 slas241h ? september 1999 ? revised september 2004 4 post office box 655303 ? dallas, texas 75265 short-form description cpu the msp430 cpu has a 16-bit risc architecture that is highly transparent to the application. all operations, other than program-flow instructions, are performed as register operations in conjunction with seven addressing modes for source operand and four addressing modes for destination operand. the cpu is integrated with 16 registers that provide reduced instruction execution time. the register-to-register operation execution time is one cycle of the cpu clock. four of the registers, r0 to r3, are dedicated as program counter, stack pointer, status register, and constant generator respectively. the remaining registers are general-purpose registers. peripherals are connected to the cpu using data, address, and control buses, and can be handled with all instructions. instruction set the instruction set consists of 51 instructions with three formats and seven address modes. each instruction can operate on word and byte data. table 1 shows examples of the three types of instruction formats; the address modes are listed in table 2. table 1. instruction word formats dual operands, source-destination e.g. add r4,r5 r4 + r5 ???> r5 single operands, destination only e.g. call r8 pc ??>(tos), r8??> pc relative jump, un/conditional e.g. jne jump-on-equal bit = 0 table 2. address mode descriptions address mode s d syntax example operation register mov rs,rd mov r10,r11 r10 ??> r11 indexed mov x(rn),y(rm) mov 2(r5),6(r6) m(2+r5)??> m(6+r6) symbolic (pc relative) mov ede,toni m(ede) ??> m(toni) absolute mov &mem,&tcdat m(mem) ??> m(tcdat) indirect mov @rn,y(rm) mov @r10,tab(r6) m(r10) ??> m(tab+r6) indirect autoincrement mov @rn+,rm mov @r10+,r11 m(r10) ??> r11 r10 + 2??> r10 immediate mov #x,toni mov #45,toni #45 ??> m(toni) note: s = source d = destination
slas241h ? september 1999 ? revised september 2004 5 post office box 655303 ? dallas, texas 75265 operating modes the msp430 has one active mode and five software selectable low-power modes of operation. an interrupt event can wake up the device from any of the five low-power modes, service the request and restore back to the low-power mode on return from the interrupt program. the following six operating modes can be configured by software: active mode am; ? all clocks are active low-power mode 0 (lpm0); ? cpu is disabled aclk and smclk remain active. mclk is disabled low-power mode 1 (lpm1); ? cpu is disabled aclk and smclk remain active. mclk is disabled dco?s dc-generator is disabled if dco not used in active mode low-power mode 2 (lpm2); ? cpu is disabled mclk and smclk are disabled dco?s dc-generator remains enabled aclk remains active low-power mode 3 (lpm3); ? cpu is disabled mclk and smclk are disabled dco?s dc-generator is disabled aclk remains active low-power mode 4 (lpm4); ? cpu is disabled aclk is disabled mclk and smclk are disabled dco?s dc-generator is disabled crystal oscillator is stopped
slas241h ? september 1999 ? revised september 2004 6 post office box 655303 ? dallas, texas 75265 interrupt vector addresses the interrupt vectors and the power-up starting address are located in the address range of 0ffffh?0ffe0h. the vector contains the 16-bit address of the appropriate interrupt handler instruction sequence. interrupt source interrupt flag system interrupt word address priority power-up external reset watchdog flash memory wdtifg keyv (see note 1) reset 0fffeh 15, highest nmi oscillator fault flash memory access violation nmiifg ofifg accvifg (see notes 1 & 4) (non)-maskable, (non)-maskable, (non)-maskable 0fffch 14 0fffah 13 0fff8h 12 comparator_a caifg maskable 0fff6h 11 watchdog timer wdtifg maskable 0fff4h 10 timer_a3 taccr0 ccifg (see note 2) maskable 0fff2h 9 timer_a3 taccr1 ccifg. taccr2 ccifg taifg (see notes 1 & 2) maskable 0fff0h 8 0ffeeh 7 0ffech 6 0ffeah 5 0ffe8h 4 i/o port p2 (eight flags; see note 3) p2ifg.0 to p2ifg.7 (see notes 1 & 2) maskable 0ffe6h 3 i/o port p1 (eight flags) p1ifg.0 to p1ifg.7 (see notes 1 & 2) maskable 0ffe4h 2 0ffe2h 1 0ffe0h 0, lowest notes: 1. multiple source flags 2. interrupt flags are located in the module 3. there are eight port p2 interrupt flags, but only six port p2 i/o pins (p2.0?5) implemented on the ?c11x1 and ?f11x1a devices . 4. (non)-maskable: the individual interrupt-enable bit can disable an interrupt event, but the general interrupt enable cannot. nonmaskable: neither the individual nor the general interrupt-enable bit will disable an interrupt event.
slas241h ? september 1999 ? revised september 2004 7 post office box 655303 ? dallas, texas 75265 special function registers most interrupt and mod ule enable bits are collected into the lowest address space. special function register bits not allocated to a functional purpose are not physically present in the device. simple software access is provided with this arrangement. interrupt enable 1 and 2 7654 0 ofie wdtie 32 1 rw-0 rw-0 rw-0 address 0h nmiie accvie rw-0 wdtie: watchdog timer interrupt enable. inactive if watchdog mo de is selected. acti ve if watchdog t imer is configured in interval timer mode. ofie: oscillator fault enable nmiie: (non)maskable interrupt enable accvie: flash access violation interrupt enable 7654 0 32 1 address 01h interrupt flag register 1 and 2 7654 0 ofifg wdtifg 32 1 rw-0 rw-1 rw-(0) address 02h nmiifg wdtifg: set on watchdog timer overflow (in watchdog mode) or security key violation. reset on v cc power-up or a reset condition at rst /nmi pin in reset mode. ofifg: flag set on oscillator fault nmiifg: set via rst /nmi-pin 7654 0 32 1 address 03h legend rw: rw-0,1: bit can be read and written. bit can be read and written. it is reset or set by puc. bit can be read and written. it is reset or set by por. rw-(0,1): sfr bit is not present in device
slas241h ? september 1999 ? revised september 2004 8 post office box 655303 ? dallas, texas 75265 memory organization msp430c1101 msp430c1111 msp430c1121 memory main: interrupt vector main: code memory size rom rom 1kb rom 0ffffh?0ffe0h 0ffffh?0fc00h 2kb rom 0ffffh?0ffe0h 0ffffh?0f800h 4kb rom 0ffffh?0ffe0h 0ffffh?0f000h information memory size flash not applicable not applicable not applicable boot memory size rom not applicable not applicable not applicable ram size 128 byte 027fh ? 0200h 128 byte 027fh ? 0200h 256 byte 02ffh ? 0200h peripherals 16-bit 8-bit 8-bit sfr 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h msp430f1101a msp430f1111a msp430f1121a memory main: interrupt vector main: code memory size flash flash 1kb flash 0ffffh?0ffe0h 0ffffh?0fc00h 2kb flash 0ffffh?0ffe0h 0ffffh?0f800h 4kb flash 0ffffh?0ffe0h 0ffffh?0f000h information memory size flash 128 byte 010ffh ? 01080h 256 byte 010ffh ? 01000h 256 byte 010ffh ? 01000h boot memory size rom 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h 1kb 0fffh ? 0c00h ram size 128 byte 027fh ? 0200h 128 byte 027fh ? 0200h 256 byte 02ffh ? 0200h peripherals 16-bit 8-bit 8-bit sfr 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h 01ffh ? 0100h 0ffh ? 010h 0fh ? 00h bootstrap loader (bsl) the msp430 bootstrap loader (bsl) enables users to program the flash memory or ram using a uart serial interface. access to the msp430 memory via the bsl is protected by user-defined password. for complete description of the features of the bsl and its implementation, see the application report features of the msp430 bootstrap loader , literature number slaa089. bsl function dw, pw & dgv package pins rge package pins data transmit 14 - p1.1 14 - p1.1 data receive 10 - p2.2 8 - p2.2
slas241h ? september 1999 ? revised september 2004 9 post office box 655303 ? dallas, texas 75265 flash memory the flash memory can be programmed via the jtag port, the bootstrap loader, or in-system by the cpu. the cpu can perform single-byte and single-word writes to the flash memory. features of the flash memory include: flash memory has n segments of main memory and two segments of information memory (a and b) of 128 bytes each. each segment in main memory is 512 bytes in size. segments 0 to n may be erased in one step, or each segment may be individually erased. segments a and b can be erased individually, or as a group with segments 0?n. segments a and b are also called information memory. new devices may have some bytes programmed in the information memory (needed for test during manufacturing). the user should perform an erase of the information memory prior to the first use. segment0 w/ interrupt vectors 0ffffh 0fe00h information memory flash main memory segment1 segment2 segment3 segment4 segment5 segment6 segment7 segmenta segmentb 0fdffh 0fc00h 0fbffh 0fa00h 0f9ffh 0f800h 0f7ffh 0f600h 0f5ffh 0f400h 0f3ffh 0f200h 0f1ffh 0f000h 010ffh 01080h 0107fh 01000h note: all segments not implemented on all devices.
slas241h ? september 1999 ? revised september 2004 10 post office box 655303 ? dallas, texas 75265 peripherals peripherals are connected to the cpu through data, address, and control busses and can be handled using all instructions. for complete module descriptions, refer to the msp430x1xx family user?s guide , literature number slau049. oscillator and system clock the clock system is supported by the basic clock module that includes support for a 32768-hz watch crystal oscillator, an internal digitally-controlled oscillator (dco) and a high frequency crystal oscillator. the basic clock module is designed to meet the requirements of both low system cost and low-power consumption. the internal dco provides a fast turn-on clock source and stabilizes in less than 6 s. the basic clock module provides the following clock signals: auxiliary clock (aclk), sourced from a 32768-hz watch crystal or a high frequency crystal. main clock (mclk), the system clock used by the cpu. sub-main clock (smclk), the sub-system clock used by the peripheral modules. digital i/o there are two 8-bit i/o ports implemented?ports p1 and p2 (only six p2 i/o signals are available on external pins): all individual i/o bits are independently programmable. any combination of input, output, and interrupt conditions is possible. edge-selectable interrupt input capability for all the eight bits of port p1 and six bits of port p2. read/write access to port-control registers is supported by all instructions. note: six bits of port p2, p2.0 to p2.5, are available on external pins ? but all control and data bits for port p2 are implemented. watchdog timer the primary function of the watchdog timer (wdt) module is to perform a controlled system restart after a software problem occurs. if the selected time interval expires, a system reset is generated. if the watchdog function is not needed in an application, the module can be configured as an interval timer and can generate interrupts at selected time intervals. comparator_a the primary function of the comparator_a module is to support precision slope analog-to-digital conversions, battery-voltage supervision, and monitoring of external analog signals.
slas241h ? september 1999 ? revised september 2004 11 post office box 655303 ? dallas, texas 75265 timer_a3 timer_a3 is a 16-bit timer/counter with three capture/compare registers. timer_a3 can support multiple capture/compares, pwm outputs, and interval timing. timer_a3 also has extensive interrupt capabilities. interrupts may be generated from the counter on overflow conditions and from each of the capture/compare registers. timer_a3 signal connections input pin number device input signal module input name module block module output signal output pin number dw, pw, dgv rge dw, pw dgv rge 13 - p1.0 13 - p1.0 taclk taclk aclk aclk timer na smclk smclk timer na 9 - p2.1 7 - p2.1 inclk inclk 14 - p1.1 14 - p1.1 ta0 cci0a 14 - p1.1 14 - p1.1 10 - p2.2 8 - p2.2 ta0 cci0b ccr0 ta0 18 - p1.5 18 - p1.5 v ss gnd ccr0 ta0 v cc v cc 15 - p1.2 15 - p1.2 ta1 cci1a 11 - p2.3 10 - p2.3 caout (internal) cci1b ccr1 ta1 15 - p1.2 15 - p1.2 v ss gnd ccr1 ta1 19 - p1.6 20 - p1.6 v cc v cc 16 - p1.3 16 - p1.3 ta2 cci2a 12 - p2.4 11 - p2.4 aclk (internal) cci2b ccr2 ta2 16 - p1.3 16 - p1.3 v ss gnd ccr2 ta2 20 - p1.7 21 - p1.7 v cc v cc
slas241h ? september 1999 ? revised september 2004 12 post office box 655303 ? dallas, texas 75265 peripheral file map peripherals with word access timer_a reserved reserved reserved reserved capture/compare register capture/compare register capture/compare register timer_a register reserved reserved reserved reserved capture/compare control capture/compare control capture/compare control timer_a control timer_a interrupt vector taccr2 taccr1 taccr0 tar tacctl2 tacctl1 tacctl0 tactl taiv 017eh 017ch 017ah 0178h 0176h 0174h 0172h 0170h 016eh 016ch 016ah 0168h 0166h 0164h 0162h 0160h 012eh flash memory flash control 3 flash control 2 flash control 1 fctl3 fctl2 fctl1 012ch 012ah 0128h watchdog watchdog/timer control wdtctl 0120h peripherals with byte access comparator_a comparator_a port disable comparator_a control 2 comparator_a control 1 capd cactl2 cactl1 05bh 05ah 059h basic clock basic clock system control 2 basic clock system control 1 dco clock frequency control bcsctl2 bcsctl1 dcoctl 058h 057h 056h port p2 port p2 selection port p2 interrupt enable port p2 interrupt edge select port p2 interrupt flag port p2 direction port p2 output port p2 input p2sel p2ie p2ies p2ifg p2dir p2out p2in 02eh 02dh 02ch 02bh 02ah 029h 028h port p1 port p1 selection port p1 interrupt enable port p1 interrupt edge select port p1 interrupt flag port p1 direction port p1 output port p1 input p1sel p1ie p1ies p1ifg p1dir p1out p1in 026h 025h 024h 023h 022h 021h 020h special function sfr interrupt flag 2 sfr interrupt flag 1 sfr interrupt enable 2 sfr interrupt enable 1 ifg2 ifg1 ie2 ie1 003h 002h 001h 000h
slas241h ? september 1999 ? revised september 2004 13 post office box 655303 ? dallas, texas 75265 absolute maximum ratings ? voltage applied at v cc to v ss ?0.3 v to 4.1 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage applied to any pin (see note) ?0.3 v to v cc +0.3 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . diode current at any device terminal 2 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (unprogrammed device) ?55 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature, t stg (programmed device) ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. note: all voltages referenced to v ss . the jtag fuse-blow voltage, v fb , is allowed to exceed the absolute maximum rating. the voltage is applied to the test pin when blowing the jtag fuse. recommended operating conditions min nom max units msp430c11x1 1.8 3.6 supply voltage during program execution, v cc (see note 1) msp430c11x1 1.8 3.6 v supply voltage during program execution, v cc (see note 1) msp430f11x1a 1.8 3.6 v supply voltage during program/erase flash memory, v cc msp430f11x1a 2.7 3.6 v supply voltage, v ss 0 v operating free-air temperature range, t a msp430x11x1(a) ?40 85 c lfxt1 crystal frequency, lf mode selected, xts=0 watch crystal 32 768 hz lfxt1 crystal frequency, f (lfxt1) (see note 1 & 2) xt1 mode selected, xts=1 ceramic resonator 450 8000 khz f (lfxt1) (see note 1 & 2) xt1 mode selected, xts=1 crystal 1000 8000 khz processor frequency f (system) (mclk signal) v cc = 1.8 v, msp430x11x1(a) dc 4.15 mhz processor frequency f (system) (mclk signal) v cc = 3.6 v, msp430x11x1(a) dc 8 mhz notes: 1. in lf mode, the lfxt1 oscillator requires a watch crystal. a 5.1m ? resistor from xout to v ss is recommended when v cc < 2.5 v. in xt1 mode, the lfxt1 and xt2 oscillators accept a ceramic resonator or crystal up to 4.15mhz at v cc 2.2 v. in xt1 mode, the lfxt1 and xt2 oscillators accept a ceramic resonator or crystal up to 8mhz at v cc 2.8 v. 2. in lf mode, the lfxt1 oscillator requires a watch crystal. in xt1 mode, lfxt1 accepts a ceramic resonator or a crystal. 1.8 v 3.6 v 2.7 v 3 v ????? ????? ????? ????? ????? ????? ????? ????? ????? note: minimum processor frequency is defined by system clock. flash program or erase operations require a minimum v cc of 2.7 v. f system (mhz) figure 1. frequency vs supply voltage, msp430x11x1(a)
slas241h ? september 1999 ? revised september 2004 14 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) supply current (into v cc ) excluding external current parameter test conditions min typ max unit t a = ?40 c to + 85 c, f (mclk) = f (smclk) = 1 mhz, v cc = 2.2 v 160 200 c11x1 a f (mclk) = f (smclk) = 1 mhz, f (aclk) = 32,768 hz v cc = 3 v 240 300 c11x1 t a = ?40 c to + 85 c, v cc = 2.2 v 1.3 2 t a = ?40 c to + 85 c, f (mclk) = f (smclk) = f (aclk) = 4096 h z v cc = 3 v 2.5 3.2 i (am) active mode t a = ?40 c to + 85 c, f mclk = f (smclk) = 1 mhz, v cc = 2.2 v 200 250 a f11x1a f mclk = f (smclk) = 1 mhz, f(aclk) = 32,768 hz, program executes in flash v cc = 3 v 300 350 f11x1a t a = ?40 c to + 85 c, program executes in flash v cc = 2.2 v 3 5 a program executes in flash f (mclk) = f (smclk) = f (aclk) = 4096 h z v cc = 3 v 11 18 c11x1 t a = ?40 c to + 85 c, f (mclk) = 0, f (smclk) = 1 mhz, v cc = 2.2 v 30 40 i (cpuoff) low-power mode, c11x1 a f (mclk) = 0, f (smclk) = 1 mhz, f(aclk) = 32,768 hz v cc = 3 v 51 60 a i (cpuoff) low-power mode, (lpm0) f11x1a t a = ?40 c to + 85 c, f (mclk) = 0, f (smclk) = 1 mhz, v cc = 2.2 v 32 45 a f11x1a a f (mclk) = 0, f (smclk) = 1 mhz, f(aclk) = 32,768 hz v cc = 3 v 55 70 i (lpm2) low-power mode, t a = ?40 c to + 85 c, f (mclk) = f (smclk) = 0 mhz, v cc = 2.2 v 11 14 a i (lpm2) low-power mode, (lpm2) a f (mclk) = f (smclk) = 0 mhz, f(aclk) = 32,768 hz, scg0 = 0 v cc = 3 v 17 22 a c11x1 t a = ?40 c to + 85 c, f (mclk) = f (smclk) = 0 mhz, v cc = 2.2 v 1.2 1.7 c11x1 a f (mclk) = f (smclk) = 0 mhz, f(aclk) = 32,768 hz, scg0 = 1 v cc = 3 v 2 2.7 low-power mode, t a = ?40 c 0.8 1.2 i (lpm3) low-power mode, (lpm3) t a = 25 c f (mclk) = 0 mhz, v cc = 2.2 v 0.7 1 a i (lpm3) (lpm3) f11x1a t a = 85 c f (mclk) = 0 mhz, f (smclk) = 0 mhz, v cc = 2.2 v 1.6 2.3 a f11x1a t a = ?40 c f (smclk) = 0 mhz, f (aclk) = 32,768 hz, scg0 = 1 1.8 2.2 t a = 25 c f (aclk) = 32,768 hz, scg0 = 1 v cc = 3 v 1.6 1.9 t a = 85 c v cc = 3 v 2.3 3.4 t a = ?40 c 0.1 0.5 c11x1 t a = 25 c f = 0 mhz, v cc = 2.2 v/3 v 0.1 0.5 i (lpm4) low-power mode, (lpm4) c11x1 t a = 85 c f (mclk) = 0 mhz, f (smclk) = 0 mhz, v cc = 2.2 v/3 v 0.4 0.8 a i (lpm4) low-power mode, (lpm4) t a = ?40 c f (smclk) = 0 mhz, f (aclk) = 0 hz, scg0 = 1 0.1 0.5 a f11x1a t a = 25 c f (aclk) = 0 hz, scg0 = 1 v cc = 2.2 v/3 v 0.1 0.5 f11x1a t a = 85 c v cc = 2.2 v/3 v 0.8 1.9 note: all inputs are tied to 0 v or v cc . outputs do not source or sink any current. current consumption of active mode versus system frequency, c version, f version i am = i am[1 mhz] f system [mhz] current consumption of active mode versus supply voltage, c version i am = i am[3 v] + 105 a/v (v cc ?3 v) current consumption of active mode versus supply voltage, f version i am = i am[3 v] + 120 a/v (v cc ?3 v)
slas241h ? september 1999 ? revised september 2004 15 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) schmitt-trigger inputs ? ports p1 and p2; (p1.0 to p1.7, p2.0 to p2.5) parameter test conditions min typ max unit v it+ positive-going input threshold voltage v cc = 2.2 v 1.1 1.5 v v it+ positive-going input threshold voltage v cc = 3 v 1.5 1.9 v v it? negative-going input threshold voltage v cc = 2.2 v 0.4 0.9 v v it? negative-going input threshold voltage v cc = 3 v 0.9 1.3 v v hys input voltage hysteresis (v it+ ? v it? ) v cc = 2.2 v 0.3 1.1 v v hys input voltage hysteresis (v it+ ? v it? ) v cc = 3 v 0.5 1 v standard inputs ? rst /nmi, jtag: tck, tms, tdi/tclk parameter test conditions min typ max unit v il low-level input voltage v cc = 2.2 v / 3 v v ss v ss +0.6 v v ih high-level input voltage v cc = 2.2 v / 3 v 0.8 v cc v cc v inputs px.x, tax parameter test conditions v cc min typ max unit port p1, p2: p1.x to p2.x, external trigger signal 2.2 v/3 v 1.5 cycle t (int) external interrupt timing port p1, p2: p1.x to p2.x, external trigger signa l for the interrupt flag, (see note 1) 2.2 v 62 ns t (int) external interrupt timing for the interrupt flag, (see note 1) 3 v 50 ns t (cap) timer_a, capture timing ta0, ta1, ta2 2.2 v 62 ns t (cap) timer_a, capture timing ta0, ta1, ta2 3 v 50 ns f (taext) timer_a clock frequency taclk, inclk t (h) = t (l) 2.2 v 8 mhz f (taext ) timer_a clock frequency externally applied to pin taclk, inclk t (h) = t (l) 3 v 10 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 2.2 v 8 mhz f (taint) timer_a clock frequency smclk or aclk signal selected 3 v 10 mhz notes: 1. the external signal sets the interrupt flag every time the minimum t (int) cycle and time parameters are met. it may be set even with trigger signals shorter than t (int) . both the cycle and timing specifications must be met to ensure the flag is set. t (int) is measured in mclk cycles. leakage current parameter test conditions min typ max unit i lkg(px.x) high-impedance leakage current port p1: p1.x, 0 7 (see notes 1, 2) v cc = 2.2 v/3 v, 50 na i lkg(px.x) high-impedance leakage current port p2: p2.x, 0 5 (see notes 1, 2) v cc = 2.2 v/3 v, 50 na notes: 1. the leakage current is measured with v ss or v cc applied to the corresponding pin(s), unless otherwise noted. 2. the leakage of the digital port pins is measured individually. the port pin must be selected for input and there must be no o ptional pullup or pulldown resistor.
slas241h ? september 1999 ? revised september 2004 16 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1 and p2; (p1.0 to p1.7, p2.0 to p2.5) parameter test conditions min typ max unit high-level output voltage i (ohmax) = ?1.5 ma v cc = 2.2 v see note 1 v cc ?0.25 v cc v oh high-level output voltage port 1 and port 2 (c11x1) i (ohmax) = ?6 ma v cc = 2.2 v see note 2 v cc ?0.6 v cc v v oh port 1 and port 2 (c11x1) port 1 (f11x1a) i (ohmax) = ?1.5 ma v cc = 3 v see note 1 v cc ?0.25 v cc v port 1 (f11x1a) i (ohmax) = ?6 ma v cc = 3 v see note 2 v cc ?0.6 v cc i (ohmax) = ?1 ma v cc = 2.2 v see note 3 v cc ?0.25 v cc v oh high-level output voltage i (ohmax) = ?3.4 ma v cc = 2.2 v see note 3 v cc ?0.6 v cc v v oh high-level output voltage port 2 (f11x1a) i (ohmax) = ?1 ma v cc = 3 v see note 3 v cc ?0.25 v cc v port 2 (f11x1a) i (ohmax) = ?3.4 ma v cc = 3 v see note 3 v cc ?0.6 v cc low-level output voltage i (olmax) = 1.5 ma v cc = 2.2 v see note 1 v ss v ss +0.25 v ol low-level output voltage port 1 and port 2 (c11x1, i (olmax) = 6 ma v cc = 2.2 v see note 2 v ss v ss +0.6 v v ol port 1 and port 2 (c11x1, f11x1a) i (olmax) = 1.5 ma v cc = 3 v see note 1 v ss v ss +0.25 v f11x1a) i (olmax) = 6 ma v cc = 3 v see note 2 v ss v ss +0.6 notes: 1. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 12 ma to hold the maximum voltage drop specified. 2. the maximum total current, i ohmax and i olmax , for all outputs combined, should not exceed 48 ma to hold the maximum voltage drop specified. 3. one output loaded at a time. output frequency parameter test conditions vcc min typ max unit f p20 p2.0/aclk, c l = 20 pf 2.2 v/3 v f system f tax output frequency ta0, ta1, ta2, c l = 20 pf internal clock source, smclk signal applied (see note 1) 2.2 v/3 v dc f system mhz f smclk = f lfxt1 = f xt1 40% 60% p1.4/smclk, f smclk = f lfxt1 = f lf 2.2 v/3 v 35% 65% p1.4/smclk, c l = 20 pf f smclk = f lfxt1/n 2.2 v/3 v 50%? 15 ns 50% 50%+ 15 ns t xdc duty cycle of o/p frequency f smclk = f dcoclk 2.2 v/3 v 50%? 15 ns 50% 50%+ 15 ns frequency p2.0/aclk, f p20 = f lfxt1 = f xt1 40% 60% p2.0/aclk, c l = 20 pf f p20 = f lfxt1 = f lf 2.2 v/3 v 30% 70% c l = 20 pf f p20 = f lfxt1/n 2.2 v/3 v 50% t tadc ta0, ta1, ta2, c l = 20 pf, duty cycle = 50% 2.2 v/3 v 0 50 ns note 1: the limits of the system clock mclk has to be met. mclk and smclk can have different frequencies.
slas241h ? september 1999 ? revised september 2004 17 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) outputs ? ports p1 and p2 (continued) figure 2 v ol ? low-level output voltage ? v 0 2 4 6 8 10 12 14 16 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma figure 3 v ol ? low-level output voltage ? v 0 5 10 15 20 25 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 typical low-level output current vs low-level output voltage t a = 25 c t a = 85 c ol i ? typical low-level output current ? ma figure 4 v oh ? high-level output voltage ? v ?14 ?12 ?10 ?8 ?6 ?4 ?2 0 0.0 0.5 1.0 1.5 2.0 2.5 v cc = 2.2 v p1.0 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma figure 5 v oh ? high-level output voltage ? v ?30 ?25 ?20 ?15 ?10 ?5 0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v cc = 3 v p1.0 typical high-level output current vs high-level output voltage t a = 25 c t a = 85 c oh i ? typical high-level output current ? ma note: one output loaded at a time.
slas241h ? september 1999 ? revised september 2004 18 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) optional resistors, individually programmable with rom code (see note 1) parameter test conditions min typ max unit r (opt1) 2.5 5 10 k ? r (opt2) 3.8 7.7 15 k ? r (opt3) 7.6 15 31 k ? r (opt4) 11.5 23 46 k ? r (opt5) resistors, individually programmable with rom code, all port pins, v cc = 2.2 v/3 v 23 45 90 k ? r (opt6) resistors, individually programmable with rom code, all port pins, values applicable for pulldown and pullup v cc = 2.2 v/3 v 46 90 180 k ? r (opt7) values applicable for pulldown and pullup 70 140 280 k ? r (opt8) 115 230 460 k ? r (opt9) 160 320 640 k ? r (opt10) 205 420 830 k ? note 1: optional resistors r optx for pulldown or pullup are not available in standard flash memory device msp430f11x1a. wake-up from lower power modes (lpmx) parameter test conditions min typ max unit t (lpm0) v cc = 2.2 v/3 v 100 ns t (lpm2) v cc = 2.2 v/3 v 100 ns f (mclk) = 1 mhz, v cc = 2.2 v/3 v 6 t (lpm3) delay time (see note 1) f (mclk) = 2 mhz, v cc = 2.2 v/3 v 6 s t (lpm3) delay time (see note 1) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6 s f (mclk) = 1 mhz, v cc = 2.2 v/3 v 6 t (lpm4) f (mclk) = 2 mhz, v cc = 2.2 v/3 v 6 s t (lpm4) f (mclk) = 3 mhz, v cc = 2.2 v/3 v 6 s note 1: parameter applicable only if dcoclk is used for mclk. ram parameter min nom max unit v (ramh) cpu halted (see note 1) 1.6 v note 1: this parameter defines the minimum supply voltage v cc when the data in the program memory ram remains unchanged. no program execution should happen during this supply voltage condition.
slas241h ? september 1999 ? revised september 2004 19 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) comparator_a (see note 1) parameter test conditions min typ max unit i (dd) caon=1, carsel=0, caref=0 v cc = 2.2 v 25 40 a i (dd) caon=1, carsel=0, caref=0 v cc = 3 v 45 60 a i (refladder/refdiode) caon=1, carsel=0, caref=1/2/3, no load at v cc = 2.2 v 30 50 a i (refladder/refdiode) caref=1/2/3, no load at p2.3/ca0/ta1 and p2.4/ca1/ta2 v cc = 3 v 45 71 a v (ic) common-mode input voltage caon =1 v cc = 2.2 v/3 v 0 v cc ?1 v v (ref025) voltage @ 0.25 v cc node v cc pca0=1, carsel=1, caref=1, no load at p2.3/ca0/ta1 and p2.4/ca1/ta2 v cc = 2.2 v/3 v 0.23 0.24 0.25 v (ref050) voltage @ 0.5v cc node v cc pca0=1, carsel=1, caref=2, no load at p2.3/ca0/ta1 and p2.4/ca1/ta2 v cc = 2.2 v/3 v 0.47 0.48 0.5 v (refvt) (see figure 6 and figure 7) pca0=1, carsel=1, caref=3, no load at p2.3/ca0/ta1 and v cc = 2.2 v 390 480 540 mv v (refvt) (see figure 6 and figure 7) no load at p2.3/ca0/ta1 and p2.4/ca1/ta2, t a = 85 c v cc = 3 v 400 490 550 mv v (offset) offset voltage see note 2 v cc = 2.2 v/3 v ?30 30 mv v hys input hysteresis caon=1 v cc = 2.2 v/3 v 0 0.7 1.4 mv t a = 25 c, overdrive 10 mv, v cc = 2.2 v 160 210 300 ns t (response lh) t a = 25 c, overdrive 10 mv, without filter: caf=0 v cc = 3 v 90 150 240 ns t (response lh) t a = 25 c, overdrive 10 mv, v cc = 2.2 v 1.4 1.9 3.4 s t a = 25 c, overdrive 10 mv, with filter: caf=1 v cc = 3 v 0.9 1.5 2.6 s t a = 25 c, overdrive 10 mv, v cc = 2.2 v 130 210 300 ns t (response hl) t a = 25 c, overdrive 10 mv, without filter: caf=0 v cc = 3 v 80 150 240 ns t (response hl) t a = 25 c, overdrive 10 mv, v cc = 2.2 v 1.4 1.9 3.4 s t a = 25 c, overdrive 10 mv, with filter: caf=1 v cc = 3 v 0.9 1.5 2.6 s notes: 1. the leakage current for the comparator_a terminals is identical to i lkg(px.x) specification. 2. the input offset voltage can be cancelled by using the caex bit to invert the comparator_a inputs on successive measurements. the two successive measurements are then summed together.
slas241h ? september 1999 ? revised september 2004 20 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 3 v figure 6. v (refvt) vs temperature, v cc = 3 v v (refvt) ? reference volts ?mv typical figure 7. v (refvt) vs temperature, v cc = 2.2 v t a ? free-air temperature ? c 400 450 500 550 600 650 ?45 ?25 ?5 15 35 55 75 95 v cc = 2.2 v v (refvt) ? reference volts ?mv typical _ + caon 0 1 v+ 0 1 caf low pass filter 2.0 s to internal modules set caifg flag caout v? v cc 1 0 v 0 figure 8. block diagram of comparator_a module overdrive v caout t (response) v+ v? 400 mv figure 9. overdrive definition
slas241h ? september 1999 ? revised september 2004 21 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) puc/por parameter test conditions min typ max unit t (por_delay) internal time delay to release por 150 250 s v cc threshold at which por t a = ?40 c 1.4 1.8 v v por v cc threshold at which por release delay time begins (see note 1) t a = 25 c 1.1 1.5 v v por release delay time begins (see note 1) t a = 85 c v cc = 2.2 v/3 v 0.8 1.2 v v (min) v cc threshold required to generate a por (see note 2) v cc |dv/dt| 1v/ms cc 0.2 v t (reset) rst /nmi low time for puc/por reset is accepted internally 2 s notes: 1. v cc rise time dv/dt 1v/ms. 2. when driving v cc low in order to generate a por condition, v cc should be driven to 200mv or lower with a dv/dt equal to or less than ?1v/ms. the corresponding rising v cc must also meet the dv/dt requirement equal to or greater than +1v/ms. vcc por v t v por v (min) por no por figure 10. power-on reset (por) vs supply voltage 0 0.2 0.6 1.0 1.2 1.8 2.0 ?40 ?20 0 20 40 60 80 temperature [ c] v por [v] 1.6 1.4 0.8 0.4 1.2 1.5 1.8 0.8 1.1 1.4 25 c max min figure 11. v por vs temperature
slas241h ? september 1999 ? revised september 2004 22 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) dco parameter test conditions min typ max unit f (dco03) r sel = 0, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 0.08 0.12 0.15 mhz f (dco03) r sel = 0, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 0.08 0.13 0.16 mhz f (dco13) r sel = 1, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 0.14 0.19 0.23 mhz f (dco13) r sel = 1, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 0.14 0.18 0.22 mhz f (dco23) r sel = 2, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 0.22 0.30 0.36 mhz f (dco23) r sel = 2, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 0.22 0.28 0.34 mhz f (dco33) r sel = 3, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 0.37 0.49 0.59 mhz f (dco33) r sel = 3, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 0.37 0.47 0.56 mhz f (dco43) r sel = 4, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 0.61 0.77 0.93 mhz f (dco43) r sel = 4, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 0.61 0.75 0.9 mhz f (dco53) r sel = 5, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 1 1.2 1.5 mhz f (dco53) r sel = 5, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 1 1.3 1.5 mhz f (dco63) r sel = 6, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 1.6 1.9 2.2 mhz f (dco63) r sel = 6, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 1.69 2 2.29 mhz f (dco73) r sel = 7, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 2.4 2.9 3.4 mhz f (dco73) r sel = 7, dco = 3, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 2.7 3.2 3.65 mhz f (dco77) r sel = 7, dco = 7, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v 4 4.5 4.9 mhz f (dco77) r sel = 7, dco = 7, mod = 0, dcor = 0, t a = 25 c v cc = 3 v 4.4 4.9 5.4 mhz f (dco47) r sel = 4, dco = 7, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v/3 v f dco40 f dco40 f dco40 mhz f (dco47) r sel = 4, dco = 7, mod = 0, dcor = 0, t a = 25 c v cc = 2.2 v/3 v f dco40 x1.7 f dco40 x2.1 f dco40 x2.5 mhz s (rsel) s r = f rsel+1 /f rsel v cc = 2.2 v/3 v 1.35 1.65 2 ratio s (dco) s dco = f dco+1 /f dco v cc = 2.2 v/3 v 1.07 1.12 1.16 ratio d t temperature drift, r sel = 4, dco = 3, mod = 0 v cc = 2.2 v ?0.31 ?0.36 ?0.40 %/ c d t temperature drift, r sel = 4, dco = 3, mod = 0 (see note 1) v cc = 3 v ?0.33 ?0.38 ?0.43 %/ c d v drift with v cc variation, r sel = 4, dco = 3, mod = 0 (see note 1) v cc = 2.2 v/3 v 0 5 10 %/v note 1: these parameters are not production tested. ?????? ?????? ?????? ?????? 2.2 v 3 v v cc max min max min f (dcox7) f (dcox0) frequency variance 012 34567 dco steps 1 f dcoclk figure 12. dco characteristics
slas241h ? september 1999 ? revised september 2004 23 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) main dco characteristics individual devices have a minimum and maximum operation frequency. the specified parameters for f ( dcox0) to f ( dcox7) are valid for all devices. all ranges selected by rsel(n) overlap with rsel(n+1): rsel0 overlaps rsel1, ... rsel6 overlaps rsel7. dco control bits dco0, dco1, and dco2 have a step size as defined by parameter s dco . modulation control bits mod0 to mod4 select how often f ( dco+1) is used within the period of 32 dcoclk cycles. the frequency f (dco) is used for the remaining cycles. the frequency is an average equal to:

dco when using r osc (see note 1) parameter test conditions v cc min nom max unit f dco , dco output frequency r sel = 4, dco = 3, mod = 0, dcor = 1, 2.2 v 1.8 15% mhz f dco , dco output frequency r sel = 4, dco = 3, mod = 0, dcor = 1, t a = 25 c 3 v 1.95 15% mhz d t , temperature drift r sel = 4, dco = 3, mod = 0, dcor = 1 2.2 v/3 v 0.1 %/ c d v , drift with v cc variation r sel = 4, dco = 3, mod = 0, dcor = 1 2.2 v/3 v 10 %/v notes: 1. r osc = 100k ? . metal film resistor, type 0257. 0.6 watt with 1% tolerance and t k = 50ppm/ c. crystal oscillator, lfxt1 parameter test conditions min typ max unit c xin input capacitance xts=0; lf mode selected. v cc = 2.2 v / 3 v 12 pf c xin input capacitance xts=1; xt1 mode selected. v cc = 2.2 v / 3 v (see note 1) 2 pf c xout output capacitance xts=0; lf mode selected. v cc = 2.2 v / 3 v 12 pf c xout output capacitance xts=1; xt1 mode selected. v cc = 2.2 v / 3 v (see note 1) 2 pf v il input levels at xin v cc = 2.2 v/3 v (see note 2) v ss 0.2 v cc v v ih input levels at xin v cc = 2.2 v/3 v (see note 2) 0.8 v cc v cc v notes: 1. requires external capacitors at both terminals. values are specified by crystal manufacturers. 2. applies only when using an external logic-level clock source. not applicable when using a crystal or resonator.
slas241h ? september 1999 ? revised september 2004 24 post office box 655303 ? dallas, texas 75265 electrical characteristics over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted) (continued) flash memory parameter test conditions v cc min nom max unit v cc(pgm/ erase) program and erase supply voltage 2.7 3.6 v f ftg flash timing generator frequency 257 476 khz i pgm supply current from v cc during program 2.7 v/ 3.6 v 3 5 ma i erase supply current from v cc during erase 2.7 v/ 3.6 v 3 7 ma t cpt cumulative program time see note 1 2.7 v/ 3.6 v 4 ms t cmerase cumulative mass erase time see note 2 2.7 v/ 3.6 v 200 ms program/erase endurance 10 4 10 5 cycles t retention data retention duration t j = 25 c 100 years t word word or byte program time 35 t block, 0 block program time for 1 st byte or word 30 t block, 1-63 block program time for each additional byte or word see note 3 21 t ftg t block, end block program end-sequence wait time see note 3 6 t ftg t mass erase mass erase time 5297 t seg erase segment erase time 4819 notes: 1. the cumulative program time must not be exceeded when writing to a 64-byte flash block. this parameter applies to all programming methods: individual word/byte write and block write modes. 2. the mass erase duration generated by the flash timing generator is at least 11.1ms ( = 5297x1/f ftg ,max = 5297x1/476khz). to achieve the required cumulative mass erase time the flash controller?s mass erase operation can be repeated until this time is met. (a worst case minimum of 19 cycles are required). 3. these values are hardwired into the flash controller?s state machine (t ftg = 1/f ftg ). jtag interface parameter test conditions v cc min nom max unit f tck tck input frequency see note 1 2.2 v 0 5 mhz f tck tck input frequency see note 1 3 v 0 10 mhz r internal internal pull-down resistance on test see note 2 2.2 v/ 3 v 25 60 90 k ? notes: 1. f tck may be restricted to meet the timing requirements of the module selected. 2. test pull-down resistor implemented in all versions. jtag fuse (see note 1) parameter test conditions v cc min nom max unit v cc(fb) supply voltage during fuse-blow condition t a = 25 c 2.5 v v fb voltage level on test for fuse-blow - ?c11x1 3.5 3.9 v v fb voltage level on test for fuse-blow - ?f11x1a 6 7 v i fb supply current into test during fuse blow 100 ma t fb time to blow fuse 1 ms notes: 1. once the fuse is blown, no further access to the msp430 jt ag/t est and emulation features is possible. the jtag block is switched to bypass mode.
slas241h ? september 1999 ? revised september 2004 25 post office box 655303 ? dallas, texas 75265 application information input/output schematic port p1, p1.0 to p1.3, input/output with schmitt-trigger en d (see note 1) (see note 2) (see note 2) (see note 1) gnd v cc p1.0 ? p1.3 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic note: x = bit/identifier, 0 to 3 for port p1 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p1sel.0 p1dir.0 p1dir.0 p1out.0 v ss p1in.0 taclk ? p1ie.0 p1ifg.0 p1ies.0 p1sel.1 p1dir.1 p1dir.1 p1out.1 out0 signal ? p1in.1 cci0a ? p1ie.1 p1ifg.1 p1ies.1 p1sel.2 p1dir.2 p1dir.2 p1out.2 out1 signal ? p1in.2 cci1a ? p1ie.2 p1ifg.2 p1ies.2 p1sel.3 p1dir.3 p1dir.3 p1out.3 out2 signal ? p1in.3 cci2a ? p1ie.3 p1ifg.3 p1ies.3 ? signal from or to timer_a notes: 1. optional selection of pullup or pulldown resistors with rom (masked) versions 2. fuses for optional pullup and pulldown resistors can only be programmed at the factory (rom versions only).
slas241h ? september 1999 ? revised september 2004 26 post office box 655303 ? dallas, texas 75265 application information port p1, p1.4 to p1.7, input/output with schmitt-trigger and in-system access features en d see note 1 see note 2 see note 2 see note 1 gnd v cc p1.4?p1.7 0 1 0 1 interrupt edge select en set q p1ie.x p1ifg.x p1irq.x interrupt flag p1ies.x p1sel.x module x in p1in.x p1out.x module x out direction control from module p1dir.x p1sel.x pad logic bus keeper tst fuse 60 k ? fuse blow control control by jtag 0 1 tdo controlled by jtag p1.x tdi p1.x tst tst tms tst tck tst controlled by jtag tst p1.x p1.x note: the test pin should be protected from potential emi and esd voltage spikes. this may require a smaller external pulldown resistor in some applications. x = bit identifier, 4 to 7 for port p1 during programming activity and during blowing of the fuse, the pin tdo/tdi is used to apply the test input for jtag circuitry. p1.7/tdi/tdo p1.6/tdi/tclk p1.5/tms p1.4/tck typical test gnd pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p1sel.4 p1dir.4 p1dir.4 p1out.4 smclk p1in.4 unused p1ie.4 p1ifg.4 p1ies.4 p1sel.5 p1dir.5 p1dir.5 p1out.5 out0 signal ? p1in.5 unused p1ie.5 p1ifg.5 p1ies.5 p1sel.6 p1dir.6 p1dir.6 p1out.6 out1 signal ? p1in.6 unused p1ie.6 p1ifg.6 p1ies.6 p1sel.7 p1dir.7 p1dir.7 p1out.7 out2 signal ? p1in.7 unused p1ie.7 p1ifg.7 p1ies.7 ? signal from or to timer_a notes: 1. optional selection of pullup or pulldown resistors with rom (masked) versions 2. fuses for optional pullup and pulldown resistors can only be programmed at the factory (rom versions only).
slas241h ? september 1999 ? revised september 2004 27 post office box 655303 ? dallas, texas 75265 application information port p2, p2.0 to p2.2, input/output with schmitt-trigger en d see note 1 see note 2 see note 2 see note 1 gnd v cc p2.0 ? p2.2 0 1 0 1 interrupt edge select en set q p2ie.x p2ifg.x p2irq.x interrupt flag p2ies.x p2sel.x module x in p2in.x p2out.x module x out direction control from module p2dir.x p2sel.x pad logic note: x = bit identifier, 0 to 2 for port p2 0: input 1: output bus keeper capd.x pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.0 p2dir.0 p2dir.0 p2out.0 aclk p2in.0 unused p2ie.0 p2ifg.0 p1ies.0 p2sel.1 p2dir.1 p2dir.1 p2out.1 v ss p2in.1 inclk ? p2ie.1 p2ifg.1 p1ies.1 p2sel.2 p2dir.2 p2dir.2 p2out.2 caout p2in.2 cci0b ? p2ie.2 p2ifg.2 p1ies.2 ? signal from or to timer_a notes: 1. optional selection of pullup or pulldown resistors with rom (masked) versions 2. fuses for optional pullup and pulldown resistors can only be programmed at the factory (rom versions only).
slas241h ? september 1999 ? revised september 2004 28 post office box 655303 ? dallas, texas 75265 application information port p2, p2.3 to p2.4, input/output with schmitt-trigger en d see note 1 see note 2 see note 2 see note 1 gnd v cc p2.3 0 1 0 1 interrupt edge select en set q p2ie.3 p2ifg.3 p2irq.3 interrupt flag p2ies.3 p2sel.3 module x in p2in.3 p2out.3 module x out direction control from module p2dir.3 p2sel.3 pad logic 0: input 1: output bus keeper capd.3 en d see note 1 see note 2 see note 2 see note 1 p2.4 1 0 1 0 interrupt edge select en set q p2ie.4 p2ifg.4 p2irq.4 interrupt flag p2ies.4 p2sel.4 module x in p2in.4 p2out.4 module x out direction control from module p2dir.4 p2sel.4 pad logic 0: input 1: output bus keeper capd.4 _ + comparator_a reference block caref caref caex p2ca caf cci1b 0 v v cc gnd pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.3 p2dir.3 p2dir.3 p2out.3 out1 signal ? p2in.3 unused p2ie.3 p2ifg.3 p1ies.3 p2sel.4 p2dir.4 p2dir.4 p2out.4 out2 signal ? p2in.4 unused p2ie.4 p2ifg.4 p1ies.4 ? signal from timer_a notes: 1. optional selection of pullup or pulldown resistors with rom (masked) versions 2. fuses for optional pullup and pulldown resistors can only be programmed at the factory (rom versions only).
slas241h ? september 1999 ? revised september 2004 29 post office box 655303 ? dallas, texas 75265 application information port p2, p2.5, input/output with schmitt-trigger and r osc function for the basic clock module en d see note 1 see note 2 see note 2 see note 1 gnd v cc p2.5 0 1 0 1 interrupt edge select en set q p2ie.5 p2ifg.5 p2irq.5 interrupt flag p2ies.5 p2sel.5 module x in p2in.5 p2out.5 module x out direction control from module p2dir.5 p2sel.5 pad logic note: dcor: control bit from basic clock module if it is set, p2.5 is disconnected from p2.5 pad bus keeper 0 1 0 1 v cc internal to basic clock module dcor dc generator 0: input 1: output capd.5 pnsel.x pndir.x direction control from module pnout.x module x out pnin.x module x in pnie.x pnifg.x pnies.x p2sel.5 p2dir.5 p2dir.5 p2out.5 v ss p2in.5 unused p2ie.5 p2ifg.5 p2ies.5 notes: 1. optional selection of pullup or pulldown resistors with rom (masked) versions 2. fuses for optional pullup and pulldown resistors can only be programmed at the factory (rom versions only).
slas241h ? september 1999 ? revised september 2004 30 post office box 655303 ? dallas, texas 75265 application information port p2, unbonded bits p2.6 and p2.7 en d 0 1 0 1 interrupt edge select en set q p2ie.x p2ifg.x p2irq.x interrupt flag p2ies.x p2sel.x module x in p2in.x p2out.x module x out direction control from module p2dir.x p2sel.x bus keeper 0 1 0: input 1: output node is reset with puc puc note: x = bit/identifier, 6 to 7 for port p2 without external pins p2sel.x p2dir.x direction control from module p2out.x module x out p2in.x module x in p2ie.x p2ifg.x p2ies.x p2sel.6 p2dir.6 p2dir.6 p2out.6 v ss p2in.6 unused p2ie.6 p2ifg.6 p2ies.6 p2sel.7 p2dir.7 p2dir.7 p2out.7 v ss p2in.7 unused p2ie.7 p2ifg.7 p2ies.7 note 1: unbonded bits 6 and 7 of port p2 can be used as software interrupt flags. the interrupt flags can only be influenced by software. they work then as a software interrupt.
slas241h ? september 1999 ? revised september 2004 31 post office box 655303 ? dallas, texas 75265 jtag fuse check mode msp430 devices that have the fuse on the test terminal have a fuse check mode that tests the continuity of the fuse the first time the jtag port is accessed after a power-on reset (por). when activated, a fuse check current, i tf , of 1 ma at 3 v, 2.5 ma at 5 v can flow from the test pin to ground if the fuse is not burned. care must be taken to avoid accidentally activating the fuse check mode and increasing overall system power consumption. when the test pin is taken back low after a test or programming session, the fuse check mode and sense currents are terminated. activation of the fuse check mode occurs with the first negative edge on the tms pin after power up or if tms is being held low during power up. the second positive edge on the tms pin deactivates the fuse check mode. after deactivation, the fuse check mode remains inactive until another por occurs. after each por the fuse check mode has the potential to be activated. the fuse check current will only flow when the fuse check mode is active and the tms pin is in a low state (see figure 13). therefore, the additional current flow can be prevented by holding the tms pin high (default condition). time tms goes low after por tms i tf i test figure 13. fuse check mode current, msp430f11x1a and msp430c11x1 note: the code and ram data protection is ensured if the jtag fuse is blown and the 256-bit bootloader access key is used. also, see the bootstrap loader section for more information.

packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) msp430c1101 active tbd call ti call ti msp430c1101ipm active tbd call ti call ti msp430f1101aidgv active tvsop dgv 20 90 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1101aidgvr active tvsop dgv 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1101aidw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1101aidwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1101aipw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1101aipwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1101airger active qfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1101airget active qfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1111aidgv active tvsop dgv 20 90 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1111aidgvr active tvsop dgv 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1111aidw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1111aidwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1111aipw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1111aipwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim MSP430F1111AIRGEr active qfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year MSP430F1111AIRGEt active qfn rge 24 250 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1121aidgv active tvsop dgv 20 90 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1121aidgvr active tvsop dgv 20 2000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1121aidw active soic dw 20 25 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1121aidwr active soic dw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1121aipw active tssop pw 20 70 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1121aipwr active tssop pw 20 2000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim msp430f1121airger active qfn rge 24 3000 green (rohs & no sb/br) cu nipdau level-2-260c-1 year msp430f1121airget active qfn rge 24 250 green (rohs & cu nipdau level-2-260c-1 year package option addendum www.ti.com 9-aug-2005 addendum-page 1
orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish msl peak temp (3) no sb/br) (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs) or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. package option addendum www.ti.com 9-aug-2005 addendum-page 2
mechanical data mpds006c february 1996 revised august 2000 post office box 655303 ? dallas, texas 75265 dgv (r-pdso-g**) plastic small-outline 24 pins shown 14 3,70 3,50 4,90 5,10 20 dim pins ** 4073251/e 08/00 1,20 max seating plane 0,05 0,15 0,25 0,50 0,75 0,23 0,13 112 24 13 4,30 4,50 0,16 nom gage plane a 7,90 7,70 38 24 16 4,90 5,10 3,70 3,50 a max a min 6,60 6,20 11,20 11,40 56 9,60 9,80 48 0,08 m 0,07 0,40 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion, not to exceed 0,15 per side. d. falls within jedec: 24/48 pins mo-153 14/16/20/56 pins mo-194

mechanical data mtss001c january 1995 revised february 1999 post office box 655303 ? dallas, texas 75265 pw (r-pdso-g**) plastic small-outline package 14 pins shown 0,65 m 0,10 0,10 0,25 0,50 0,75 0,15 nom gage plane 28 9,80 9,60 24 7,90 7,70 20 16 6,60 6,40 4040064/f 01/97 0,30 6,60 6,20 8 0,19 4,30 4,50 7 0,15 14 a 1 1,20 max 14 5,10 4,90 8 3,10 2,90 a max a min dim pins ** 0,05 4,90 5,10 seating plane 0 8 notes: a. all linear dimensions are in millimeters. b. this drawing is subject to change without notice. c. body dimensions do not include mold flash or protrusion not to exceed 0,15. d. falls within jedec mo-153
important notice texas instruments incorporated and its subsidiaries (ti) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete. all products are sold subject to ti?s terms and conditions of sale supplied at the time of order acknowledgment. ti warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with ti?s standard warranty. testing and other quality control techniques are used to the extent ti deems necessary to support this warranty. except where mandated by government requirements, testing of all parameters of each product is not necessarily performed. ti assumes no liability for applications assistance or customer product design. customers are responsible for their products and applications using ti components. to minimize the risks associated with customer products and applications, customers should provide adequate design and operating safeguards. ti does not warrant or represent that any license, either express or implied, is granted under any ti patent right, copyright, mask work right, or other ti intellectual property right relating to any combination, machine, or process in which ti products or services are used. information published by ti regarding third-party products or services does not constitute a license from ti to use such products or services or a warranty or endorsement thereof. use of such information may require a license from a third party under the patents or other intellectual property of the third party, or a license from ti under the patents or other intellectual property of ti. reproduction of information in ti data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties, conditions, limitations, and notices. reproduction of this information with alteration is an unfair and deceptive business practice. ti is not responsible or liable for such altered documentation. resale of ti products or services with statements different from or beyond the parameters stated by ti for that product or service voids all express and any implied warranties for the associated ti product or service and is an unfair and deceptive business practice. ti is not responsible or liable for any such statements. following are urls where you can obtain information on other texas instruments products and application solutions: products applications amplifiers amplifier.ti.com audio www.ti.com/audio data converters dataconverter.ti.com automotive www.ti.com/automotive dsp dsp.ti.com broadband www.ti.com/broadband interface interface.ti.com digital control www.ti.com/digitalcontrol logic logic.ti.com military www.ti.com/military power mgmt power.ti.com optical networking www.ti.com/opticalnetwork microcontrollers microcontroller.ti.com security www.ti.com/security telephony www.ti.com/telephony video & imaging www.ti.com/video wireless www.ti.com/wireless mailing address: texas instruments post office box 655303 dallas, texas 75265 copyright ? 2005, texas instruments incorporated

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